The dynamic random access memory (DRAM) device 1 represented by the diagram of FIG. 1 stores digital data in an arrangement of memory cells 3. An arrangement of memory cells is called an array. The cells 3 are arranged in the array in a configuration of intersecting rows 5 and columns 6. The rows 5 are also referred to as wordlines 5. Each memory cell comprises a storage capacitor (not shown) capable of holding a charge and a metal-oxide semiconductor field effect transistor (MOSFET) (not shown) for accessing the capacitor charge; hereinafter this transistor is referred to as an access transistor. The charge is a voltage potential referred to as a data bit and is typified as either a high voltage or a low voltage. Therefore, the memory has two states; often thought of as the true logic state and the complementary logic state. The data bit is amplified and latched to the digit lines 7 by sense amplifier 8.
There are two options available in a DRAM memory; a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is either transferred from the digit lines 7 to Input/Output lines, (I/O), 9 in the read mode; or transferred from the I/O lines 9 to the digit lines 7 in the write mode. In either case, the data is transferred through MOSFETs 10 used as switching devices and called decode transistors. For each bit of data stored, its true logic state is available at a first I/O line 11 and its complementary logic state is available at a second I/O line 13, designated I/O complement. For purposes of this discussion, I/O and I/O complement lines are often referred to as just I/O lines 9. Although each cell 3 is only connected to one digit line 7 through an activated access transistor, each cell 3 is electrically referenced to two digit lines 7, referred to as a digit line pair 15, through the sense amplifiers 8. The digit line pair 15 comprises the "digit line" 17 for coupling true data and the "digit bar line" 19 for coupling complementary data. Typically, the digit line 17 is referred to as digit and the digit bar line 19 is referred to as digit bar. The digit line pair 15 couples the true and complementary data between the selected cell 3 and the I/O lines 9.
In order to read from or write to a cell 3, the particular cell 3 in question must be selected or sometimes referred to as "addressed." A particular cell 3 is selected when the row decoder 21 activates a wordline 5 and the column decoder 23 activates a column 6. The electrical intersection of the activated wordline 5 and activated column 6 determines which cell 3 has been selected.
A supply potential V.sub.cc and a ground reference potential are available to the circuitry of the memory device. Between cycles of cell selection it is necessary to equilibrate the digit lines of each digit line pair 15 in a memory array to the same voltage, usually V.sub.cc /2. This equilibration of the digit lines is often referred to as the precharge cycle. Equilibrate circuitry (not shown) parallel with the sense amplifier essentially shorts the digit lines together and holds them at V.sub.cc /2. This equilibration is necessary so that the digit lines 7 are ready to receive data during the next cycle.
In order to facilitate an understanding of the present invention, pertinent aspects of a typical write operation to a single cell are explained below with reference to FIG. 2. FIG. 2 more fully depicts the circuitry relevant to two digit line pairs 15A and 15B of the digit line pairs 15 shown in FIG. 1. The numbers pertinent to components in FIG. 1 are relevant to similar components in FIG. 2.
Digits 17A and 17B are connected to memory cells 3A and 3B respectively and are accessed through row 5A. Digit bars 19A and 19B are connected to memory cells 3C and 3D respectively and are accessed through row 5B. Therefore, memory cells 3A and 3B store data in true form and memory cells 3C and 3D store data in complementary or inverse form. The p sense amplifiers 8A and 8B and the n sense amplifiers 8C and 8D latch data on the digit line pairs 15A and 15B respectively during read and write operations.
During standby switching transistors 24 comprising the pull up p-type MOSFETs (p switching transistors) 25 and the pull down n-type MOSFET (n switching transistor) 26 are off and the data remains stored in cells 3A through 3D. During a write or read operation all of the p 25 and n 26 transistors are actuated. The p switching transistors 25 are actuated by a low signal applied to their gates. Once actuated, the p switching transistors 25 couple the supply voltage V.sub.cc 27 to the circuit. The n switching transistor 26 is actuated by a high signal applied to its gate. Once actuated, the n switching transistor 26 couples the ground reference potential 28 to the circuit.
For example, assume cell 3A is selected for a write operation. An active output from the row decoder activates wordline 5A. The active wordline 5A actuates the cells' 3A and 3B access transistors 29A and 29B pertinent to wordline 5A, while access transistors 29C and 29D pertinent to inactive wordline 5B remain deactivated. The switching transistors 24 are actuated and digit 17A is latched to the true data stored in cell 3A While digit bar 19A is latched to the complement of the true data. Similarly, digit 17B is latched to the true data stored in cell 3B while digit bar 19B is latched to the complement of the true data. Next the column decoder activates column 6A which in turn actuates decode transistors 10A. Column 6B remains inactive since it was not activated by the column decoder. Consequently decode transistors 10B remain off. In a write mode the input data is coupled through the actuated decode transistors 10A from the I/O lines 9 to the digit line pair 15A where the input data overwrites the data previously latched to digit line pair 15A. The data on digit line pair 15B is not disturbed since decode transistors 10B are off.
Continuing with the example, since the digit lines 7 are sitting at approximately V.sub.cc /2 in standby, the data coupled to the digit lines through the activated access transistors 29A and 29B effect a change in voltage on digits 17A and 17B. Taking a specific example, assume the true data stored in memory cell 3A is low. Then the voltage on digit 17A is pulled below V.sub.cc /2. Digit bar 19A remains at V.sub.cc /2 since it is not directly connected to cell 3A; this leaves digit bar 19A at a relatively higher voltage potential than digit 17A. When switching transistors 24 are actuated, the sources 35 of cross coupled p-type sense amplifier MOSFETs (p sense amplifier transistors) 36 of the p sense amplifiers 8A and 8B are at V.sub.cc 27, the sources 37 of cross coupled n-type sense amplifier MOSFETs (n sense amplifier transistors) 39 of the n sense amplifier 8C and 8D are at ground 28, and sense amplifiers 8A through 8D latch the data stored in the memory cells to the digit line pairs 15A and 15B. The relative high on digit bar 19A turns on the n sense amplifier transistor 39A on digit 17A, pulling it to ground 28. The low on the digit 17A turns on the p sense amplifier transistor 36A on digit bar 19A pulling digit bar 19A high. Similar action occurs on digit pair 15B where the final state of digit 17B depends on the original data stored in cell 3B and coupled onto digit 17B through access transistor 29B. Thus, the sense amplifiers ensure that digits 17A and 17B and digit bars 19A and 19B retain the correct voltage by pulling the low to ground 28 and by pulling the high to V.sub.cc 27. Assume the data on I/O 11 is high and I/O complement 13 is low. When column 6A activates decode transistors 10A, the low on I/O complement overwrites the high on 19A. The sense amplifiers 8A and 8C now latch opposite the previous state with a high on digit 17A charging the storage capacitor 41 to a voltage greater than V.sub.cc /2 through the activated access transistor 29A.
Next, the access transistors 29A and 29B turn off, the capacitor 41 remains charged, the switching transistors 24 turn off, the column 6A is deactivated and the digit line pair 15 equilibrates to approximately V.sub.cc /2.
If the cell is on the digit bar 19, it stores complementary data and, conversely, if the cell is on the digit 17, it stores true data. During a read mode the sense amps latch digit and digit bar to the true and complementary value of the originally stored data. The data is then coupled to the I/O lines through activated decode transistors 10A or 10B.
Video RAMs having one megabit and higher densities may include a flash write mode. Flash write is a one cycle set or clear of an entire row. Typically a set is a high logic state and a clear is a low logic state. In a flash write operation all of the cells pertinent to a selected wordline simultaneously receive substantially identical data.
An integrated circuit (I.C.) memory products, such as DRAM and Video RAM, the amount of available memory is often referred to as the density. Density describes the total amount of memory fabricated on the circuit (i.e., 1 meg, 4 meg, and so forth).
It is common to provide memory products which contain a large number of storage cells. Each storage cell is addressable by a unique row and column address. Therefore n row and m column addresses can access an array of n times m storage cells. Such a memory device would accept data for storage through an input often called the "D" input. Data read from the memory would be presented on an output called the "Q" output.
Memory vendors often provide more than one configuration of a certain density product to better suit the needs of the consumer.
In one popular variation the memory is split into 4, 8, 16 or more equal segments, and these segments are accessed in parallel. In this variation less row and column addresses are required since each sub array is only a portion of the total memory density, and since the sub arrays typically respond to the same row and column address. Such a configuration multiplies the "D" and "Q" pins required for transferring data into and out of the I.C. In order to keep the package small the input and output functions are commonly combined to share the same pin which is now called a "DQ" pin. Each "DQ" pin services one of the aforementioned sub arrays which is then often referred to as a "DQ plane."
This division of the total density into equal sided and commonly addressed DQ planes is very useful in certain systems which use IC memory. The various available configurations are often referred to as "by one", "by four", "by eight" and so forth. For example a 1 meg VRAM may be split into 4 DQ planes, DQs, and is referred to as a 256K by four memory.
This division of the total density into equal sided and commonly addressed DQ planes is very useful in certain systems which use IC memory. The various available configurations are often referred to as "by one", "by four", "by eight" and so forth. For example a 1 meg VRAM may be split into 4 DQ planes, DQs, and referred to as a 256K by four memory. In the flash write operation mode all 512 cells on the selected row in each array (DQ) are set or cleared. In a typical read/write operation of a single memory cell one cell in each DQ is read from or written to.
Flash write is typically accomplished by modifying the column decode circuitry to access all columns simultaneously and by storing the set or clear data appearing on the I/O lines in all of the cells of the selected wordline. Typically video RAM specifications include a color register for each DQ to allow individual set and reset of each DQ. The individual color registers necessitate repeating the flash write control logic for each DQ.
There are at least two disadvantages in modifying the column decode circuitry in order to perform flash write. The circuitry is cumbersome and power consumption is high. The video RAM column decode circuitry includes considerations for block write, split transfers, by-four/by-eight options and page mode. Further column decode modifications for flash write tend to make the column decode circuitry even more cumbersome. Since previous data has already been latched by the sense amps to the cells, the previous data in all of the cells must be overwritten during flash write in the same manner the data was originally written into the cell. Power consumption is high in order to overwrite all columns in a given row simultaneously.